Memory circuit having non-volatile memory cell and methods of using

ABSTRACT

One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.

Notice: More than one reissue application has been filed for U.S. Pat.No. 9,672,935. The reissue applications are the present application andU.S. patent application Ser. No. 16/267,278, filed on Feb. 4, 2019,which is a continuation reissue of the present application.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of the filing date of U.S.provisional application No. 62/065,241, filed on Oct. 17, 2014, which isincorporated herein by reference in its entirety for all purposes.

BACKGROUND

Field

In some aspects, the disclosure relates to electronics and, morespecifically but not exclusively, to programmable non-volatile memorycircuits.

Related Art

This section introduces aspects that may help facilitate a betterunderstanding of the disclosure. Accordingly, the statements of thissection are to be read in this light and are not to be understood asadmissions about what is prior art or what is not prior art.

Non-volatile (NV) memory is used for configuration pattern storage forprogrammable logic devices such as field-programmable gate arrays(FPGAs). When this NV memory is external to the FPGA, the pattern istransferred to the FPGA's internal configuration static random-accessmemory (SRAM) through regular data pins. There are some productapplications, however, where the NV memory block is internally embeddedwithin the FPGA chip itself, so as to provide secure, independentconfiguration storage even when the FPGA is powered down. This memorypattern is normally transferred internally during chip power-up as an“initialization” sequence, with the data transfer most often takingplace in the conventional fashion—as if the configuration pattern wasexternally presented to the FPGA's configuration controller even thoughthe source is actually on chip.

SUMMARY

One aspect relates to a memory circuit comprising: a programmablenon-volatile memory (NVM) cell configured to generate an NVM outputsignal indicative of a program state of the NVM cell comprising a firstanti-fuse device (e.g., N1), a first select device (e.g., N2) connectedin series with the first anti-fuse device at a first node, and a firstpass device (e.g., N5) and a programmable volatile memory (VM) cellconfigured to receive the NVM output signal at a VM input node and togenerate a VM output signal indicative of the program state of the VMcell, wherein the first pass device is connected between the first nodeand the VM input nod.

A further aspect relates to a method for operating a memory circuitcomprising configuring the VM cell by pre-programming the VM cell tohave a first programmed state independent of the NVM output signal; andthen configuring the VM cell using the NVM cell such that, when the NVMcell is not programmed, the NVM output signal does not change the VMcell from the first programmed state; and when the NVM cell isprogrammed, the NVM output signal does change the VM cell to a secondprogrammed state different from the first programmed state.

A method can involve, prior to configuring the VM cell, programming theNVM cell by turning off the first pass device; and turning on the firstselect device to apply a programmable voltage level across a gate oxidelayer of the first anti-fuse device to create a permanent breakdown paththrough the gate oxide layer of the first anti-fuse device. The methodcan involve programming by turning off the first select device applyinga read voltage to a gate of the first anti-fuse device, and turning onthe first pass device, such that, when the NVM cell is programmed, thevoltage at the VM input node is changed using sufficient current flowthrough the gate oxide layer of the blown first anti-fuse device by anamount sufficient to flip the VM output signal.

An article of manufacture comprising an FPGA fabricated entirely in astandard CMOS process with distributed SRAM configuration cells where atleast a subset of the SRAM configuration cells have an associated andlocal non-volatile memory cell that is capable of programming itsassociated SRAM cell.

A further aspect relates to a NV memory cell for loading configurationdata into a respective cell of volatile configuration memory. The NVmemory cell is provided with its respective cell of volatileconfiguration memory and comprises a programmable voltage dividercomprising a pair of anti-fuse devices coupled in series, wherein in afirst programmed state, an output node is driven by a shorted voltageapplied to the output node of the NV memory cell through one of the pairof anti-fuse devices and is on one side of a common-mode voltage, and ina second programmed state, the output node is driven by a shortedvoltage applied to the output node of the NV memory cell through theother anti-fuse device of the pair and is on the other side of thecommon-mode voltage for the NVM cell.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments and implementations of the disclosure will become more fullyapparent from the following detailed description, the appended claims,and the accompanying drawings in which like reference numerals identifysimilar or identical elements.

FIG. 1 is a schematic circuit diagram of a memory circuit for storing atleast one bit of information, according to one embodiment of theinvention;

FIG. 2 is a set of waveforms representing a suitable sequence ofvoltages used to write and read a bit value into and out of the volatilememory (VM) cell of FIG. 1;

FIG. 3 is a set of waveforms representing a suitable sequence ofvoltages used to program a bit value into the non-volatile memory (NVM)cell of FIG. 1;

FIG. 4 is a set of waveforms representing a suitable sequence ofvoltages used to transfer the stored bit value from the programmed NVMcell to the VM cell of FIG. 1;

FIG. 5 is a schematic circuit diagram of a memory circuit for storingone bit of information, according to another embodiment of theinvention;

FIG. 6 is a set of waveforms representing a suitable sequence ofvoltages used to program a bit value of 1 into (the previouslyunprogrammed) NVM cell of FIG. 5;

FIG. 7 is a set of waveforms representing a suitable sequence ofvoltages used to transfer the stored bit value from the NVM cell to theVM cell of FIG. 5;

FIG. 8 is a schematic circuit diagram of a memory circuit for storing upto two bits of information, according to another embodiment of theinvention; and

FIG. 9 is a schematic circuit diagram of a memory circuit with enhancedtestability, according to another embodiment of the invention.

DETAILED DESCRIPTION

Detailed illustrative embodiments of the present invention are disclosedherein. However, specific structural and functional details disclosedherein are merely representative for purposes of describing exampleembodiments of the present invention. The present invention may beembodied in many alternate forms and should not be construed as limitedto only the embodiments set forth herein. Further, the terminology usedherein is for the purpose of describing particular embodiments only andis not intended to be limiting of example embodiments of the invention.

As used herein, the singular forms “a,” “an,” and “the,” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It further will be understood that the terms “comprises,”“comprising,” “includes,” and/or “including,” specify the presence ofstated features, steps, or components, but do not preclude the presenceor addition of one or more other features, steps, or components. It alsoshould be noted that in some alternative implementations, thefunctions/acts noted may occur out of the order noted in the figures.For example, two figures shown in succession may in fact be executedsubstantially concurrently or may sometimes be executed in the reverseorder, depending upon the functionality/acts involved.

The time taken for initialization of an FPGA can be in the hundreds ofmilliseconds, especially for more-complex programmable devices. Thelatency incurred from this initialization delay can be detrimental tosystem operation. In addition, the energy (power times duration) of thisinitialization sequence can be so significant that power-reductionapproaches, which include power-gating of the FPGA configurationstorage, do not give a net improvement in energy usage, even at moderatepower-cycle frequencies. Therefore, it is advantageous to utilize anapproach which reduces both the power and the duration of thisinitialization process.

Current methods to reduce the initialization latency are generally basedon parallelization of the transfer circuitry, which reduces the overalldelay but does not affect the total energy and thus giving no advantagetowards achieving power reduction during initialization. Moreover, thelatency issue is improved, but not eliminated.

FIG. 1 is a schematic circuit diagram of a memory circuit 100 forstoring at least one bit of information, according to one embodiment ofthe invention. Memory circuit 100 will typically be one of manyinstances of similar memory circuits distributed over an integratedcircuit, such as an FPGA. As described in further detail below, variousvoltage signals are applied to the different input nodes of memorycircuit 100 to selectively store one bit of information into the memorycircuit and then subsequently read that stored bit of information fromthe memory circuit, where the bit of information is represented by thevoltage levels at the output node Q, the complementary output node QB,and the read-sense node RS.

Depending on the logic applied downstream of the memory circuit 100, a(relatively) high voltage level at node Q, a corresponding (relatively)low voltage level at node QB, and a corresponding (relatively) highvoltage level at node RS may be interpreted as either a 1 or a 0, whilethe opposite voltage levels will be interpreted as the other bit value.For simplicity of description, the following discussion assumes that abit value of 1 is represented by high voltages at nodes NV_OUT, Q, andRS, while a bit value of 0 is represented by low voltages at thosenodes. Those skilled in that art will understand that an integratedcircuit can be implemented using the complementary logic convention.

As shown in FIG. 1, memory circuit 100 has two memory cells configuredtogether: a programmable, differential, non-volatile memory (NVM) cell110 and a programmable, volatile memory (VM) cell 120, where VM cell 120is an SRAM cell with a latch architecture. NVM cell 110 comprises N-type(e.g., transistor) devices N1-N6, while VM cell 120 comprises N-type(e.g., transistor) devices N7-N9, inverters INV1 and INV2, andtransmission gate TG.

NVM cell 110 can be programmed to present either a (relatively) highvoltage level (i.e., bit value 1) or a (relatively) low voltage level(i.e., bit value 0) at the NVM-cell output node NV_OUT. In particular,to program NVM cell 110 to present a high voltage level at node NV_OUT,a suitable sequence of programming voltages can be applied to (thepreviously unprogrammed) NVM cell 110 to result in a breakdown of therelatively thin gate oxide layer of anti-fuse device N1 resulting in apermanent conduction path through that gate oxide layer. In that case,when a suitable sequence of transfer voltages are applied to NVM cell110, the output node NV_OUT will be driven high.

Alternatively, to program NVM cell 110 to present a low voltage level atnode NV_OUT, a different, suitable sequence of programming voltages canbe applied to (the previously unprogrammed) NVM cell 110 to result in abreakdown of the relatively thin gate oxide layer of anti-fuse device N4resulting in a permanent conduction path through that gate oxide layer.In that case, when the same, suitable sequence of transfer voltages areapplied to NVM cell 110, the output node NV_OUT will be driven low.

VM cell 120 can also be programmed to present either high voltage levelsor low voltage levels at the VM-cell output nodes Q and RS andcorresponding a low or high voltage level at the complementary VM-celloutput node QB. In particular and for example, to program VM cell 120 topresent a high voltage level (i.e., bit value 1) at node RS, a suitablesequence of write voltages can be applied to VM cell 120 to latch in ahigh voltage level at the input of inverter INV1. In that case, when asuitable sequence of read voltages are applied to VM cell 120, theoutput node RS will be driven high.

Alternatively, to program VM cell 120 to present a low voltage level(i.e., bit value 0) at node RS, a different, suitable set of writevoltages can be applied to VM cell 120 to latch in a low voltage levelat the input of inverter INV1. In that case, when the same, suitablesequence of read voltages are applied to VM cell 120, the output node RSwill be driven low.

VM cell 120 can also be programmed by transferring the bit value storedin NVM cell 110 into VM cell 120 by applying a suitable sequence oftransfer voltages to both NVM cell 110 and VM cell 120. Note that thebit value transferred from NVM cell 110 into VM cell 120 can besubsequently changed by re-programming the VM cell 120 as describedpreviously.

FIG. 2 is a set of waveforms representing a suitable sequence ofvoltages used to write and read a bit value into and out of VM cell 120of FIG. 1. In particular, the waveforms of FIG. 2 represent thefollowing sequence of operations: (i) program VM cell 120 by writing abit value of 0 into the VM cell, (ii) then read the stored bit value 0from the VM cell, (iii) then re-program the VM cell by writing a bitvalue of 1 into the VM cell, and (iv) then read the stored bit value 1from the VM cell. During these operations, the (programmed orunprogrammed) NVM cell 110 is disabled and isolated from VM cell 120 bysetting all of the following voltage levels low (e.g., to 0V): PROG_EN,COL_SEL_BAR, VP1, VP2, and LOAD.

In particular, as shown in FIG. 2, at time t0, the integrated circuit ispowered off and, at time t1, the integrated circuit is powered on withthe power supply voltage VCC rising from 0V to its operating level. Tostore the bit value 0 into VM cell 120, with the data voltage DATA andthe latch voltage LATCH both low, the write-select voltage WRITE_SEL isdriven high at time t2, which turns on the write device N7, which allowsthe low DATA voltage to appear at the input of inverter INV1. This, inturn, drives the output of inverter INV1 (i.e., node QB) high and theoutput of inverter INV2 (i.e., node Q) low. Prior to this time, thevoltages at nodes QB and Q were indefinite.

At time t3, the latch voltage LATCH is driven high, which turns on thetransmission gate TG, which enables the low voltage at node Q to be fedback to the input of inverter INV1. At time t4, the voltage WRITE_SEL isdriven low, which turns off device N7 and latches the bit value 0 intoVM cell 120.

To read the bit value 0 from VM cell 120, at time t5, the read-selectvoltage READ_SEL is driven high, which turns on the read device N8. Withnode QB high, device N9 will also be on, which drives node RS low. Attime t6, the voltage READ_SEL is driven low, thereby ending this readoperation of VM cell 120. Note that, when READ_SEL is driven low, theread device N8 is turned off, and node RS is driven high throughresistor R1.

To re-program VM cell 120 to store the bit value 1, at time t7, the datavoltage DATA is driven high, and, at time t8, the latch voltage LATCH isdriven low to turn off the gate TG and isolate the input to inverterINV1 from node Q. At time t9, the write-select voltage WRITE_SEL isdriven high to turn on the write device N7 and allow the high DATAvoltage to appear at the input of inverter INV1. This, in turn, drivesnode QB low and node Q high. At time t10, the latch voltage LATCH isdriven high to turn on gate TG and enable the high voltage at node Q tobe fed back to the input of inverter INV1. At time t11, the voltageWRITE_SEL is driven low to turn off device N7 and latch the bit value 1into VM cell 120.

To read the bit value 1 from VM cell 120, at time t12, the read-selectvoltage READ_SEL is driven high, which turns on the read device N8. Withnode QB low, device N9 will be off, which allows node RS to stay high.At time t13, the voltage READ_SEL is driven low, thereby ending thissecond read operation of VM cell 120.

FIG. 3 is a set of waveforms representing a suitable sequence ofvoltages used to program a bit value into NVM cell 110 of FIG. 1. Duringthis operation, all of the following voltage levels are set low: DATA,LATCH, WRITE_SEL, READ_SEL, LOAD, and COL_SEL_BAR, such that the VM cell120 is disabled and isolated from NVM cell 110. Note that VM cell 120does not have to be disabled in order to program NVM cell 110; it issufficient for VM cell 120 to be isolated from NVM cell 110.

FIG. 3 represents two different scenarios in a single timing diagram:(i) the waveforms for programming the NVM cell 110 to have a bit valueof 1 (in which case, the first programming voltage VP1 is driven highwhile the second programming voltage VP2 remains low) and (ii) thewaveforms for programming the NVM cell 110 to have a bit value of 0 (inwhich case, the first programming voltage VP1 remains low while thesecond programming voltage VP2 is driven high).

At time t0, the integrated circuit is powered off and, at time t1, theintegrated circuit is powered on with the power supply voltage VCCrising from 0V to its operating level. At time t2, the program-enablevoltage PROG_EN is driven high, which turns on access devices N2 and N3.To store a bit value of 1 into NVM cell 110, at time t3, the voltage VP1is driven to a high programming voltage level VPP, which is greater thanVCC, while the voltage VP2 remains low (not explicitly shown in FIG. 3).With VP1 at VPP and VP2 and COL_SEL_BAR both at 0V, the voltage acrossthe gate oxide layer of anti-fuse device N4 will be about 0V, while thevoltage across the gate oxide layer of anti-fuse device N1 will be aboutVPP, resulting in the permanent breakdown of that relatively thin gateoxide layer. At time t4, VP1 is driven low, and, at time t5, PROG_EN isdriven low, ending this particular programming operation. At this point,the anti-fuse device N1 has been blown, and the NVM cell 110 has beenpermanently programmed with the bit value 1.

Alternatively, to store a bit value of 0 into NVM cell 110, at time t3,VP2 is driven to VPP, while VP1 remains low (not explicitly shown inFIG. 3). In this case, with VP2 at VPP and VP1 and COL_SEL_BAR both at0V, the voltage across the gate oxide layer of anti-fuse device N1 willbe about 0V, while the voltage across the gate oxide layer of anti-fusedevice N4 will be about VPP, resulting in the permanent breakdown ofthat relatively thin gate oxide layer. At time t4, VP2 is driven low,and, at time t5, PROG_EN is driven low, ending this particular programoperation. At this point, the anti-fuse device N4 has been blown, andthe NVM cell 110 has been permanently programmed with the bit value 0.

FIG. 4 is a set of waveforms representing a suitable sequence ofvoltages used to transfer the stored bit value from the programmed NVMcell 110 to VM cell 120 of FIG. 1. During this operation, all of thefollowing voltage levels are set low: PROG_EN, VP2, DATA, WRITE_SEL,READ_SEL, and COL_SEL_BAR, while VP1 is at VCC. FIG. 4 presents twodifferent waveforms for the voltage at node NV_OUT: (i) one for thesituation in which device N1 was previously blown and (ii) another forthe situation in which device N4 was previously blown.

At time t0, the integrated circuit is powered off and, at time t1, theintegrated circuit is powered on with the power supply voltage VCCrising from 0V to its operating level. At time t2, the transfer-enablevoltage LOAD is driven high, which turns on transfer devices N5 and N6.Prior to time t2, the voltage at node NV_OUT is indeterminate. Aftertime t2, with devices N5 and N6 on, node NV_OUT will be driven eitherhigh or low depending on the programming of NVM cell 110. In particular,if NVM cell 110 is programmed with a bit value 1, then node NV_OUT willbe driven high through turned-on transfer device N5 and the broken gateoxide layer of blown anti-fuse device N1. Alternatively, if NVM cell 110is programmed with a bit value 0, then node NV_OUT will be driven lowthrough turned-on transfer device N6 and the broken gate oxide layer ofblown anti-fuse device N4. At time t3, the voltage LATCH is driven highto turn on transmission gate TG and latch the transferred bit value intoVM cell 120. At time t4, LOAD is driven low, ending this transferoperation. At this point, the VM cell 120 is isolated from the NVM cell110 and latched with the transferred bit value, which will appear atoutput node Q. Note that, to read the latched value at node RS, the readoperation of FIG. 2 can be performed.

The various operations represented in FIGS. 2-4 can be used to performvarious functions. At the time that the NVM cell 110 is programmed, itis desirable to verify that the desired bit value has been successfullystored in the NVM cell. As such, as soon as the program operation ofFIG. 3 has been performed to program the NVM cell 110, the transferoperation of FIG. 4 can be performed to transfer the stored bit valuefrom the NVM cell 110 into the VM cell 120, then the read operation ofFIG. 2 can be performed to read the transferred bit value from the VMcell 120 at node RS, and then processing (e.g., external to memorycircuit 100) can be performed to verify that the desired bit value hasbeen successfully stored in the NVM cell 110. Similarly, to verify thatVM cell 120 is operating properly, the write and read operationsoperation of FIG. 2 can be performed intermittently to determine whethera single event upset (SEU) incident has occurred that changes the bitvalue stored in VM cell 120.

Note that, in typical integrated circuits, the output nodes Q and QBwill be used for on-line operations, while the output node RS will bereserved for circuit testing and programming verification.

Because the VM cell 120 can be isolated from the NVM cell 110, the VMcell 120 can be selectively programmed and re-programmed both before andafter an NVM-stored bit value has been transferred from the NVM cell 110to the VM cell 120. Furthermore, even after the VM cell 120 has beenre-programmed to have a different bit value, the transfer operation canbe repeated to re-program the VM cell 120 with the NVM-stored bit value.This functionality is useful in many integrated circuit applications.

On the other hand, there may be integrated circuits for whichVM-programmability is not needed. In that case, it might not benecessary to be able to transfer and latch an NVM-stored bit value fromNVM cell 110 into a volatile memory cell, like VM cell 120, that canretain the value after the NVM cell 110 has been isolated. As such, inan alternative embodiment, some or all of the transmission gate TG andthe devices N7-N9 may be omitted. In that case, inverters INV1 and INV2may be said to form volatile memory circuitry that is not a programmableVM cell per se. As such, after the NVM cell 110 has been programmed, aslong as appropriate NVM transfer voltages are applied, the NVM-storedbit value will be continuously presented at the output node Q and itscomplement at the output node QB.

NVM cell 110 can be said to function as a programmable resistor-dividernetwork. Before either N1 or N4 is blown, with transfer devices N5 andN6 on, the divided voltage at node NV_OUT will be midway between thevoltages at VP1 and VP2 with both N1 and N4 functioning as capacitors.If N1 is blown, then the divided voltage at node NV_OUT will shifttowards the voltage at VP1 with N1 functioning as a resistor and N4still functioning as a capacitor. On the other hand, if instead N4 isblown, then the divided voltage at node NV_OUT will shift towards thevoltage at VP2 with N4 functioning as a resistor and N1 stillfunctioning as a capacitor.

Although memory circuit 100 has been described as storing either a bitvalue of 1 by blowing anti-fuse device N1 or a bit value of 0 by blowinganti-fuse device N4, memory circuit 100 can also be operated in adifferent mode. In particular, memory circuit 100 can be programmed tostore a first bit value by selectively blowing or not blowing anti-fusedevice N1. At some later time, memory circuit 100 can be re-programmedto store a second bit value, independent of the first bit value, byblowing anti-fuse device N1 (if it was not previously blown) and thenselectively blowing or not blowing anti-fuse device N4. Note that thissequence can be reversed by storing the initial bit value usinganti-fuse device N4 and then the subsequent bit value using anti-fusedevice N1.

When multiple instances of memory circuit 100 are used to store a singleset of configuration data, such capability effectively squares theprobability of a failure. In particular, if one of the memory circuitsfails because its first anti-fuse device was not sufficiently blown,then all of the memory circuits can be programmed a second time usingthe other anti-fuse device. In that case, the programming of the secondanti-fuse device will correct the faulty programming of the failedmemory circuit and reinforce the programming of the remaining, correctlyprogrammed memory circuits The chances of the same memory circuit beingincorrectly programmed twice is the square of its chances of beingincorrectly programmed the first time alone.

FIG. 5 is a schematic circuit diagram of a memory circuit 500 forstoring one bit of information, according to another embodiment of theinvention. Memory circuit 500 is analogous to memory circuit 100 of FIG.1, except that, instead of having the differential NVM cell 110, memorycircuit 500 has a single-sided NVM cell 510 comprising only devices N1,N2, and N5, which are similar to the corresponding devices in NVM cell110. The VM cell 520 of memory circuit 500 is identical to the VM cell120 of FIG. 1 and can be written to and read from using the samewaveforms of FIG. 2.

Unlike NVM cell 110 of FIG. 1, which has no default stored bit value,NVM cell 510 has a default stored bit value of 0 (i.e., corresponding toa relatively low voltage level at the NVM output node NV_OUT). As such,the programming of an “unprogrammed” NVM cell 110 involves the storingof a bit value of 1 into the NVM cell, in particular, by blowing theanti-fuse device N1 by breaking its gate oxide layer.

FIG. 6 is a set of waveforms representing a suitable sequence ofvoltages used to program a bit value of 1 into (the previouslyunprogrammed) NVM cell 510 of FIG. 5. During this operation, all of thefollowing voltage levels are set low: DATA, LATCH, WRITE_SEL, READ_SEL,LOAD, and COL_SEL_BAR, such that VM cell 520 is disabled and isolatedfrom NVM cell 510. Note that VM cell 520 does not have to be disabled inorder to program NVM cell 510; it is sufficient for VM cell 520 to beisolated from NVM cell 510.

At time t0, the integrated circuit is powered off and, at time t1, theintegrated circuit is powered on with the power supply voltage VCCrising from 0V to its operating level. At time t2, the program-enablevoltage PROG_EN is driven high, which turns on access device N2. At timet3, the program voltage VP1 is driven to the high programming voltagelevel VPP. With VP1 at VPP and COL_SEL_BAR at 0V, the voltage across thegate oxide layer of anti-fuse device N1 will be about VPP, resulting inthe permanent breakdown of that relatively thin gate oxide layer. Attime t4, VP1 is driven low, and, at time t5, PROG_EN is driven low,ending the program operation. At this point, the anti-fuse device N1 hasbeen blown, and the NVM cell 510 has been permanently programmed withthe bit value 1.

FIG. 7 is a set of waveforms representing a suitable sequence ofvoltages used to transfer the stored bit value from NVM cell 510 to VMcell 520 of FIG. 5. During this operation, all of the following voltagelevels are set low: PROG_EN, DATA, READ_SEL, and COL_SEL_BAR. Note that,because NVM cell 510 has a default stored bit value of 0, before theNVM-stored bit value is transferred from the NVM cell into VM cell 520,the VM cell is “pre-programmed” to have the bit value 0. As such, if NVMcell 510 still has its default stored bit value of 0 (i.e., N1 has notbeen blown), then, when the transfer operation of FIG. 7 is subsequentlyperformed, VM cell 520 will retain its pre-programmed bit value of 0.If, however, NVM cell 510 has been programmed to have a stored bit valueof 1 (i.e., N1 has been blown), then, when the transfer operation ofFIG. 7 is subsequently performed, the VM cell 520 will be re-programmedwith a bit value of 1.

As in FIG. 4, FIG. 7 presents two different waveforms for the voltage atnode NV_OUT: one for the situation in which device N1 was not previouslyblown (i.e., NVM cell 510 was not previously programmed and thereforeretains its default bit value 0) and one for the situation in whichdevice N1 was previously blown (i.e., NVM cell 510 was previouslyprogrammed to store the bit value 1).

In particular, at time t0, the integrated circuit is powered off and, attime t1, the integrated circuit is powered on with the power supplyvoltage VCC rising from 0V to its operating level. At time t2, thevoltage VP1 is driven to the supply voltage level VCC. At time t3, thewrite-enable voltage WRITE_SEL is driven high, which will turn on writedevice N7. Prior to time t3, the voltage at the NVM-cell output nodeNV_OUT was indeterminate. Since DATA is low, turning on the write deviceN7 drives the node NV_OUT low.

At time t4, the transfer-enable voltage LOAD is driven high, which turnson transfer device N5. At time t4, with device N5 on, node NV_OUT willbe driven depending on the programming of NVM cell 510. In particular,if NVM cell 510 is not programmed (i.e., device N1 is not blown), thenthe voltage at node NV_OUT will remain low. Alternatively, if NVM cellis programmed (i.e., device N1 is blown), then the voltage at nodeNV_OUT will rise slightly but will remain relatively low due to thegreater resistance of the blown device N1 than the turned-on device N7.

At time t5, WRITE_SEL is driven low, thereby turning off device N7 andisolating the node NV_OUT from the data signal DATA. If NVM cell 510 isnot programmed, then the voltage at node NV_OUT will still remain low.Alternatively, if NVM cell 510 is programmed, then the voltage at nodeNV_OUT will begin to rise as charge flows through the blown device N1and the turned-on device N5 to node NV_OUT. After a sufficient amount oftime (t-delay), the voltage at node NV_OUT will have risen to asufficiently high level to ensure that the data has been transferredfrom NVM cell 510 into VM cell 520. After that time delay, at time t6,the latch signal LATCH is driven high to turn on the transmission gateTG and latch in the transferred bit value. During the first transferafter programming, in order to verify that the NVM cell 510 has beenproperly programmed, a margin may be subtracted from the t-delay valueto decrease the programmed N1 resistance required to properly sense andlatch a bit value of 1.

At time t7, LOAD is driven low to isolate the VM cell 520 from the NVMcell 510, and, at time t8, the voltage VCC can be removed from the gateof device N1, ending the transfer operation. At this point, the VM cell120 is latched with the transferred bit value, which will appear atoutput node Q. Note that, to read the latched value at node RS, the readoperation of FIG. 2 can be performed.

Similar to memory circuit 100 of FIG. 1, the various operationsrepresented in FIGS. 2, 6, and 7 can be used to perform similarfunctions for memory circuit 500.

Note that, in alternative embodiments of memory circuits 100 and 500,the series-connected transistors N8 and N9 may be connected to the nodeQ, instead of the node QB, with a corresponding inversion of the logicapplied to interpret the corresponding voltage level.

A set of NVM cells, such as one or more instances of NVM cell 110 ofFIG. 1 and/or one or more instances of NVM cell 510 of FIG. 5, can beprogrammed to store configuration data for an integrated circuit, suchas an FPGA. When the FPGA is initially powered up, the configurationdata can be transferred from those NVM cells to corresponding VM cells.By distributing and co-locating instances of the NVM cells withcorresponding instances of the VM cells throughout the FPGA, the amountof energy used during such configuration operations and the time that istakes to perform those operations can both be significantly lower thanfor comparable integrated circuits that use co-located arrays of NVMcells to store and transfer configuration data to distributed VM cells.As such, certain embodiments of this invention provide low-energy,distributed (zero-latency) NVM cells with minimal penalty in terms ofboth silicon area and process complexity. In general, memory circuits ofthe invention may provide one or more of the following advantages:

-   -   Differential comparison with unprogrammed NVM cell maximizes        yield and system-level reliability;    -   “Live at power-up” capability;    -   Elimination of the power supply energy associated with        initialization from a separate memory store;    -   Power-gating of configuration bit cells without the penalty of        re-initialization power and time;    -   Compatibility with lower supply voltages (no retention issues);        and    -   Incremental extension to two or more configuration images which        may be selected at run time.

FIG. 8 is a schematic circuit diagram of a memory circuit 800 forstoring up to two bits of information, according to another embodimentof the invention. Memory circuit 800 is analogous to memory circuit 100of FIG. 1, except that, instead of having a single transfer-enablesignal LOAD controlling both transfer devices N5 and N6, NVM cell 810 ofmemory circuit 800 has two independent, transfer-enable signals LOAD1and LOAD2 respectively controlling transfer devices N5 and N6. The VMcell 820 of memory circuit 800 is identical to the VM cell 120 of FIG. 1and can be written to and read from using the same waveforms of FIG. 2.Memory circuit 800 can be used to independently store two different bitvalues: (1) a first bit value by selectively blowing or not blowinganti-fuse device N1 and (2) a second bit value by selectively blowing ornot blowing anti-fuse device N4.

FIG. 9 is a schematic circuit diagram of a memory circuit 900 withenhanced testability, according to another embodiment of the invention.Memory circuit 900 is analogous to memory circuit 100 of FIG. 1, exceptthat, instead of having a single program-enable signal PROG_ENcontrolling both access devices N2 and N3, NVM cell 910 of memorycircuit 900 has two independent, program-enable signals PROG_EN1 andPROG_EN2 respectively controlling access devices N2 and N3. The VM cell920 of memory circuit 900 is identical to the VM cell 120 of FIG. 1 andcan be written to and read from using the same waveforms of FIG. 2.Memory circuit 900 can be used to independently test the device chain ofN2 and N5 from the device chain of N3 and N6, by applying suitablevoltages to PROG_EN1, PROG_EN2, and COL_SEL_BAR.

Although the invention has been described in the context of NVM cellsthat rely on anti-fuse devices to vary resistance levels, the inventioncan also be implemented in the context of NVM cells that rely on fusedevices to vary resistance levels. For example, suitable resistors thatare susceptible to permanent electromigration when large voltagedifferentials are applied can be used as programmable devices in NVMcells of the invention. In either case, an NVM cell of the invention hasone or more programmable devices that can be programmed to program adesired bit value into the NVM cell by varying one or more resistancelevels in the NVM cell that alter the output voltage of the NVM cellthat is presented during a transfer operation.

The invention has been described in the context of memory circuitsimplemented using N-type devices. Those skilled in the art willunderstand that the invention can also be implemented in the context ofmemory circuits implemented using P-type devices.

Memory circuits of the invention can be fabricated using the standardcomplementary metal-oxide semiconductor (CMOS) process flow and inparticular one that does not have process steps for forming flash cells.Since the anti-fuse devices N1 and N4 function as programmablecapacitors, the anti-fuse devices can be fabricated as either capacitorsor MOS transistors. Similarly, access devices N2 and N3 and/or transferdevices NS and N6 can be implemented using types of switches other thanindividual transistors. Note that, when transfer devices N5 and N6 aretransistors, the LOAD voltage needs to be sufficiently greater than thesupply voltage VCC applied to the anti-fuse devices N1 and N4 in orderto turn on N5 and N6. The devices described in this application can bemanufactured with bulk CMOS technology, as well as silicon-on-insulator(SOI) technology.

Also for purposes of this description, the terms “couple,” “coupling,”“coupled,” “connect,” “connecting,” or “connected” refer to any mannerknown in the art or later developed in which energy is allowed to betransferred between two or more elements, and the interposition of oneor more additional elements is contemplated, although not required.Conversely, the terms “directly coupled,” “directly connected,” etc.,imply the absence of such additional elements.

Signals and corresponding terminals, nodes, ports, or paths may bereferred to by the same name and are interchangeable for purposes here.

Transistors are typically shown as single devices for illustrativepurposes. However, it is understood by those with skill in the art thattransistors will have various sizes (e.g., gate width and length) andcharacteristics (e.g., threshold voltage, gain, etc.) and may consist ofmultiple transistors coupled in parallel to get desired electricalcharacteristics from the combination. Further, the illustratedtransistors may be composite transistors.

Integrated circuits have become increasingly complex. Entire systems areconstructed from diverse integrated circuit sub-systems. Describing suchcomplex technical subject matter at an appropriate level of detailbecomes necessary. In general, a hierarchy of concepts is applied toallow those of ordinary skill to focus on details of the matter beingaddressed.

Describing portions of a design (e.g., different functional units withinan apparatus or system) according to functionality provided by thoseportions is often an appropriate level of abstraction, since each ofthese portions may themselves comprise hundreds of thousands, hundredsof millions, or more elements. When addressing some particular featureor implementation of a feature within such portion(s), it may beappropriate to identify substituent functions or otherwise characterizesome sub-portion of that portion of the design in more detail, whileabstracting other sub-portions or other functions.

A precise logical arrangement of the gates and interconnect (a netlist)implementing a portion of a design (e.g., a functional unit) can bespecified. How such logical arrangement is physically realized in aparticular chip (how that logic and interconnect is laid out in aparticular design) may differ in different process technologies and/orfor a variety of other reasons. Circuitry implementing particularfunctionality may be different in different contexts, and so disclosureof a particular circuit may not be the most helpful disclosure to aperson of ordinary skill. Also, many details concerning implementationsare often determined using design automation, proceeding from ahigh-level logical description of the feature or function to beimplemented. In various cases, describing portions of an apparatus orsystem in terms of its functionality conveys structure to a person ofordinary skill in the art. As such, it is often unnecessary and/orunhelpful to provide more detail concerning a portion of a circuitdesign than to describe its functionality.

Functional modules or units may be composed of circuitry, where suchcircuitry may be fixed function, configurable under program control orunder other configuration information, or some combination thereof.Functional modules themselves thus may be described by the functionsthat they perform, to helpfully abstract how some of the constituentportions of such functions may be implemented. In some situations,circuitry, units, and/or functional modules may be described partiallyin functional terms, and partially in structural terms. In somesituations, the structural portion of such a description may bedescribed in terms of a configuration applied to circuitry or tofunctional modules, or both.

Configurable circuitry is effectively circuitry or part of circuitry foreach different operation that can be implemented by that circuitry, whenconfigured to perform or otherwise interconnected to perform eachdifferent operation. Such configuration may come from or be based oninstructions, microcode, one-time programming constructs, embeddedmemories storing configuration data, and so on. A unit or module forperforming a function or functions refers, in some implementations, to aclass or group of circuitry that implements the functions or functionsattributed to that unit. Identification of circuitry performing onefunction does not mean that the same circuitry, or a portion thereof,cannot also perform other functions concurrently or serially.

Although circuitry or functional units may typically be implemented byelectrical circuitry, and more particularly, by circuitry that primarilyrelies on transistors fabricated in a semiconductor, the disclosure isto be understood in relation to the technology being disclosed. Forexample, different physical processes may be used in circuitryimplementing aspects of the disclosure, such as optical, nanotubes,micro-electrical mechanical elements, quantum switches or memorystorage, magnetoresistive logic elements, and so on. Although a choiceof technology used to construct circuitry or functional units accordingto the technology may change over time, this choice is an implementationdecision to be made in accordance with the then-current state oftechnology.

Embodiments according to the disclosure include non-transitory machinereadable media that store configuration data or instructions for causinga machine to execute, or for configuring a machine to execute, or fordescribing circuitry or machine structures (e.g., layout) that canexecute or otherwise perform, a set of actions or accomplish a statedfunction, according to the disclosure. Such data can be according tohardware description languages, such as HDL or VHDL, in RegisterTransfer Language (RTL), or layout formats, such as GDSII, for example.

Unless explicitly stated otherwise, each numerical value and rangeshould be interpreted as being approximate as if the word “about” or“approximately” preceded the value or range.

It will be further understood that various changes in the details,materials, and arrangements of the parts which have been described andillustrated in order to explain embodiments of this invention may bemade by those skilled in the art without departing from embodiments ofthe invention encompassed by the following claims.

In this specification including any claims, the term “each” may be usedto refer to one or more specified characteristics of a plurality ofpreviously recited elements or steps. When used with the open-ended term“comprising,” the recitation of the term “each” does not excludeadditional, unrecited elements or steps. Thus, it will be understoodthat an apparatus may have additional, unrecited elements and a methodmay have additional, unrecited steps, where the additional, unrecitedelements or steps do not have the one or more specified characteristics.

The use of figure numbers and/or figure reference labels in the claimsis intended to identify one or more possible embodiments of the claimedsubject matter in order to facilitate the interpretation of the claims.Such use is not to be construed as necessarily limiting the scope ofthose claims to the embodiments shown in the corresponding figures.

Reference herein to “one embodiment” or “an embodiment” means that aparticular feature, structure, or characteristic described in connectionwith the embodiment can be included in at least one embodiment of theinvention. The appearances of the phrase “in one embodiment” in variousplaces in the specification are not necessarily all referring to thesame embodiment, nor are separate or alternative embodiments necessarilymutually exclusive of other embodiments. The same applies to the term“implementation.”

The embodiments covered by the claims in this application are limited toembodiments that (1) are enabled by this specification and (2)correspond to statutory subject matter. Non-enabled embodiments andembodiments that correspond to non-statutory subject matter areexplicitly disclaimed even if they fall within the scope of the claims.

What is claimed is:
 1. An article of manufacture comprising a memorycircuit comprising: volatile output circuitry (VOC); and a programmablenon-volatile memory (NVM) cell configured to generate an NVM outputsignal indicative of a program state of the NVM cell, the NVM cellcomprising: a first anti-fuse device non-volatile memory element; asecond anti-fuse device non-volatile memory element; a first selectdevice connected in series with the first anti-fuse device non-volatilememory element at a first node, wherein the first select device has afirst terminal and a second terminal; a second select device connectedin series with the second anti-fuse device non-volatile memory elementat a second node, wherein the second select device has a first terminaland a second terminal, wherein the first select device's first terminalis connected to the second select device's first terminal, and whereinthe first select device's second terminal is connected to the secondselect device's second terminal; a first pass device connected betweenthe first node and a VOC input node of the volatile output circuitry andusable to selectively pass a voltage at the first node to the VOC inputnode; and a second pass device connected between the second node and theVOC input node and usable to selectively pass a voltage at the secondnode to the VOC input node, wherein the volatile output circuitry isconnected to receive the NVM output signal from the NVM cell at the VOCinput node and generate a VOC output signal indicative of the programstate of the NVM cell.
 2. The article of claim 1, wherein the VOCcomprises a first inverter (e.g., INV1) comprising an input to receivethe NVM output signal and to generate a first inverted signal at anoutput as the VOC output signal.
 3. The article of claim 1, wherein thevolatile output circuitry is an SRAM cell, wherein the firstnon-volatile memory element is configured to be programmed by applying afirst programmable voltage on the first non-volatile memory element, andwherein the second non-volatile memory element is configured to beprogrammed by applying a second programmable voltage on the secondnon-volatile element.
 4. The article of claim 1, wherein: the firstnon-volatile memory element is a first anti-fuse device and the secondnon-volatile memory element is a second anti-fuse device; the NVM cellis programmable to have a first programmed state by (i) turning off thefirst pass device and (ii) turning on the first select device to apply aprogrammable voltage level across a gate oxide layer of the firstanti-fuse device to create a permanent breakdown path through the gateoxide layer of the first anti-fuse device; the NVM cell is programmableto have a second programmed state different from the first programmedstate by (i) turning off the second pass device and (ii) turning on thesecond select device to apply a programmable voltage level across a gateoxide layer of the second anti-fuse device to create a permanentbreakdown path through the gate oxide layer of the second anti-fusedevice; and the volatile output circuitry is drivable using the NVM cellby (i) turning off the first and second select devices, (ii) applyingread voltages to the first and second anti-fuse devices' gates, and(iii) turning on the first and second pass devices to pass a shortedvoltage at the first and second nodes to the VOC input node.
 5. Thearticle of claim 4, wherein the volatile output circuitry is drivableby: programming the NVM cell to have either the first or secondprogrammed state; and then driving the volatile output circuitry usingthe NVM cell such that: if the NVM cell is programmed in the firstprogrammed state, then the NVM output signal drives the volatile outputcircuitry based on the first programmed state; and if the NVM cell isprogrammed in the second programmed state, then the NVM output signaldrives the volatile output circuitry based on the second programmedstate.
 6. The article of claim 4, wherein the NVM cell in operationimplements a programmable voltage divider wherein in the firstprogrammed state, the shorted voltage is on one side of a common-modevoltage for the NVM cell and in the second programmed state, the shortedvoltage is on the other side of the common-mode voltage for the NVMcell.
 7. The article of claim 1, wherein: the first and second selectdevices are controllable by a common program-enable control signal; andwherein the first and second pass devices are controllable by a commontransfer-enable control signal; and wherein the first pass device isdirectly connected to the second pass device.
 8. The article of claim 1,wherein: the first and second select devices are controllable by acommon program-enable control signal; the first select device isdirectly connected in series with the first non-volatile memory elementat the first node; the first select device is directly connected to onlyone non-volatile memory element; the second select device is directlyconnected in series with the second non-volatile memory element at thesecond node; the second select device is directly connected to only onenon-volatile memory element; and the first and second pass devices arecontrollable by independent transfer-enable control signals.
 9. Thearticle of claim 1, wherein: the first and second select devices arecontrollable by independent program-enable control signals; and thefirst and second pass devices are controllable by a commontransfer-enable control signal.
 10. The article of claim 1, wherein thememory circuit is part of an integrated circuit comprising multipleinstances of the memory circuit distributed over the integrated circuit,wherein, for each instance of the memory circuit, the NVM cell isco-located with the volatile output circuitry.
 11. The article of claim10, wherein the integrated circuit is a field-programmable gate array.12. A method for operating a programmable Non-Volatile Memory (NVM) cellconfigured to generate an NVM output signal indicative of a programstate of the NVM cell, the NVM cell comprising: a first anti-fuse devicenon-volatile memory element; a second anti-fuse device non-volatilememory element; a first select device connected in series with the firstanti-fuse device non-volatile memory element at a first node; a secondselect device connected in series with the second anti-fuse devicenon-volatile memory element at a second node; a first pass deviceconnected between the first node and a NVM output node of the volatileoutput circuitry and usable to selectively pass a voltage at the firstnode to the NVM output node; and a second pass device connected betweenthe second node and the NVM output node and usable to selectively pass avoltage at the second node to the NVM output node, the method comprisingreading a bit value from the NVM cell by: turning off the first selectdevice; applying a read voltage to the first anti-fuse device'snon-volatile memory element's gate; and turning on the first pass deviceto pass a the voltage at the first node to the NVM output node, wherein:when the first anti-fuse device is blown non-volatile memory element isprogrammed, the voltage at the first node passed to the NVM output nodewill be at a first level; when the first anti-fuse device is not blownnon-volatile memory element is not programmed, the voltage at the firstnode passed to the NVM output node will be at a second level differentfrom the first level; and turning off the first select device comprisesturning off the first and the second select devices; applying a readvoltage to the first anti-fuse device's non-volatile memory element gatecomprises applying read voltages to the gates of the first and thesecond anti-fuse devices non-volatile memory elements; and turning onthe first pass device comprises turning on the first and the second passdevices to pass a shorted voltage at the first and second nodes to theNVM output node, wherein: if the first anti-fuse device is blownnon-volatile memory element is programmed and the second anti-fusedevice is not blown non-volatile memory element is not programmed, theshorted voltage passed to the NVM output node will be at a the firstlevel; and if the first anti-fuse device is not blown non-volatilememory element is not programmed and the second anti-fuse device isblown non-volatile memory element is programmed, the shorted voltagepassed to the NVM output node will be at a the second level differentfrom the first level.
 13. The method of claim 12, wherein the NVM cellfunctions as a programmable voltage divider such that: when the firstanti-fuse device is blown non-volatile memory element is programmed andthe second anti-fuse device is not blown non-volatile memory element isnot programmed, the shorted voltage is on one side of a common-modevoltage for the NVM cell and when the first anti-fuse device is notblown non-volatile memory element is not programmed and the secondanti-fuse device is blown non-volatile memory element is programmed, theshorted voltage is on the other side of the common-mode voltage for theNVM cell.
 14. A method for operating a programmable Non-Volatile Memory(NVM) cell configured to generate an NVM output signal indicative of aprogram state of the NVM cell, the NVM cell comprising: a firstanti-fuse device non-volatile memory element; a second anti-fuse devicenon-volatile memory element; a first select device connected in serieswith the first anti-fuse device non-volatile memory element at a firstnode; a second select device connected in series with the secondanti-fuse device non-volatile memory element at a second node; a firstpass device connected between the first node and a NVM output node ofthe volatile output circuitry and usable to selectively pass a voltageat the first node to the NVM output node; and a second pass deviceconnected between the second node and the NVM output node and usable toselectively pass a voltage at the second node to the NVM output node,the method comprising reading a bit value from the NVM cell by: turningoff the first select device; applying a read voltage to the firstanti-fuse device's non-volatile memory element's gate; and turning onthe first pass device to pass a the voltage at the first node to the NVMoutput node, wherein: when the first anti-fuse device is blownnon-volatile memory element is programmed, the voltage at the first nodepassed to the NVM output node will be at a first level; when the firstanti-fuse device is not blown non-volatile memory element is notprogrammed, the voltage at the first node passed to the NVM output nodewill be at a second level different from the first level; reading another bit value from the NVM cell by: turning off the second selectdevice; applying a read voltage to the second anti-fuse device'snon-volatile memory element's gate; and turning on the second passdevice to pass a the voltage at the second node to the NVM output node,wherein: if the second anti-fuse device is blown non-volatile memoryelement is programmed, then the voltage at the second node passed to theNVM output node will be at a third level; and if the second anti-fusedevice is not blown non-volatile memory element is not programmed, thenthe voltage at the second node passed to the NVM output node will be ata fourth level different from the third level.
 15. A method foroperating a programmable Non-Volatile Memory (NVM) cell configured togenerate an NVM output signal indicative of a program state of the NVMcell, the NVM cell comprising: a first anti-fuse device non-volatilememory element; a second anti-fuse device non-volatile memory element; afirst select device connected in series with the first anti-fuse devicenon-volatile memory element at a first node; a second select deviceconnected in series with the second anti-fuse device non-volatile memoryelement at a second node; a first pass device connected between thefirst node and a NVM output node of the volatile output circuitry andusable to selectively pass a voltage at the first node to the NVM outputnode; and a second pass device connected between the second node and theNVM output node and usable to selectively pass a voltage at the secondnode to the NVM output node, the method comprising reading a bit valuefrom the NVM cell by: turning off the first select device; applying aread voltage to the first anti-fuse device's non-volatile memory elementgate; and turning on the first pass device to pass a the voltage at thefirst node to the NVM output node, wherein: when the first anti-fusedevice is blown non-volatile memory element is programmed, the voltageat the first node passed to the NVM output node will be at a firstlevel; when the first anti-fuse device is not blown non-volatile memoryelement is not programmed, the voltage at the first node passed to theNVM output node will be at a second level different from the firstlevel; and prior to reading the bit value from the NVM cell, programmingthe bit value into the NVM cell by: turning off the first pass device;and turning on the first select device to apply a programmable voltagelevel across a gate oxide layer of the first anti-fuse devicenon-volatile memory element to create a permanent breakdown path throughthe gate oxide layer of the first anti-fuse device non-volatile memoryelement.
 16. The method of claim 14, further comprising, prior toreading an other bit value from the NVM cell, programming the other bitvalue into the NVM cell by: turning off the second pass device; andturning on the second select device to apply a programmable voltagelevel across a gate oxide layer of the second anti-fuse devicenon-volatile memory element to create a permanent breakdown path throughthe gate oxide layer of the second anti-fuse device non-volatile memoryelement.
 17. The method of claim 12, further comprising controlling thefirst and second select devices by a common program-enable controlsignal and controlling the first and second pass devices by a commontransfer-enable control signal.
 18. The method of claim 12, furthercomprising controlling the first and second select devices by a commonprogram-enable control signal and controlling the first and second passdevices by separate and independent transfer-enable control signals. 19.The method of claim 12, further comprising controlling the first andsecond select devices are by independent program-enable control signalsand controlling the first and second pass devices by a commontransfer-enable control signal.
 20. An article of manufacture comprisinga memory circuit comprising: a programmable non-volatile memory (NVM)cell configured to generate an NVM output signal indicative of a programstate of the NVM cell, the NVM cell comprising a first anti-fuse devicenon-volatile memory element, a first select device connected in serieswith the first anti-fuse device non-volatile memory element at a firstnode, and a first pass device; a programmable volatile memory (VM) cellconfigured to receive the NVM output signal at a VM input node and togenerate a VM output signal indicative of the program state of the VMcell, wherein the first pass device is connected between the first nodeand the VM input node and usable to selectively pass a voltage at thefirst node to the VM input node, and control logic configured to (i)program the NVM cell by turning off the first pass device and turning onthe first select device to apply a program voltage level across a gateoxide layer of the first anti-fuse device non-volatile memory element tocreate a permanent breakdown path through the gate oxide layer and to(ii) cause the VM cell to be configured by the programmed NVM cell byturning off the first select device, applying a read voltage to a gateof the first anti-fuse device non-volatile memory element, and turningon the first pass device to change the voltage at the VM input nodeusing sufficient current flow through the gate oxide layer of the firstanti-fuse device non-volatile memory element by an amount sufficient toflip the VM output signal.
 21. The article of claim 20, wherein when theNVM cell is not programmed, (i) the first anti-fuse device is not blownnon-volatile memory element is not programmed, (ii) the NVM outputsignal is insufficiently definite for use in programming the VM cell,and (iii) the VM cell is programmable independent of the NVM outputsignal; and when the NVM cell is programmed, (i) the first anti-fusedevice is blown non-volatile memory element is programmed and (ii) theNVM output signal is sufficiently definite for use in programming the VMcell.
 22. The article of claim 20, wherein the VM cell is configurableby pre-programming the VM cell to have a first programmed stateindependent of the NVM output signal; and then configuring the VM cellusing the NVM cell such that: if the NVM cell is not programmed, thenthe NVM output signal does not change the VM cell from the firstprogrammed state; and if the NVM cell is programmed, then the NVM outputsignal does change the VM cell to a second programmed state differentfrom the first programmed state.
 23. The article of claim 20, whereinthe memory circuit is part of an integrated circuit comprising multipleinstances of the memory circuit distributed over the integrated circuit,wherein, for each instance of the memory circuit, the NVM cell isco-located with the VM cell.